GitHub - Subv/VHDL_CPU: 16-bit CPU with 16 registers and a 3-stage pipeline written in VHDL for the Computer Structure I class of 2015-03 Universidad del Norte Colombia

== 16 bit custom CPU in VHDL ==

16-bit CPU with 16 registers and a 3-stage pipeline written in VHDL for the Computer Structure I class of 2015-03 Universidad del Norte Colombia

Prototyped in the Altera DE2 board with a Cyclone II processor. Register values are shown in the LCD display of the Altera DE2 board.

Written by Sebastian "Subv" Valle.

Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
CPU.qpf		CPU.qpf
CPU.qsf		CPU.qsf
CPU.qws		CPU.qws
CPU.vhd		CPU.vhd
LCD.vhd		LCD.vhd
README.md		README.md
RegisterFileTypePackage.vhd		RegisterFileTypePackage.vhd

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