stm32h7: Fix Protected user SRAM placement and attributes.

[13022591351]

Summary

• Make STM32H7 Protected user heap placement consistently use SRAM_END,
  which represents the primary SRAM selected for the active M7/M4 chip
  configuration.
• Remove the fixed SRAM123_END placement that is inconsistent with heap
  sizing and is undefined for dual-core M7 and M4 configurations.
• Map Protected user data and heap SRAM as Normal, cacheable, and
  non-shareable so LDREX/STREX synchronization uses the CPU-local exclusive
  monitor on STM32H7.
• Keep dual-core RPTUN SRAM unaffected: its shared region is mapped separately
  with explicit shareable attributes.

Impact

• New feature: NO. This fixes STM32H7 Protected memory placement and MPU
  attributes.
• User adaptation: NO.
• Build process: NO.
• Hardware: YES. Only STM32H7 Protected builds are affected. Flat builds
  are unchanged. Dual-core shared RPTUN SRAM keeps its existing mapping.
• Documentation: Public API documentation is not affected; source comments
  document the mapping and dual-core exception.
• Security: NO reduction in privilege separation. User access permissions
  remain P:RW/U:RW; only the SRAM memory attributes change.
• Compatibility: The Protected user heap now resides in the SRAM region
  selected by the board/chip configuration instead of a fixed D2 boundary.

Testing

Build host:

• Linux 6.8.0-60-generic, x86_64
• GNU Arm Embedded Toolchain 10.3.1 20210824

Target:

• ARM Cortex-M7, STM32H7, PX4 FMUv6C
• Apache NuttX master 850805d70c88b0d63d4364d7110ce5363d2448ee
• Protected user heap in AXI SRAM, write-through data cache enabled
• Runtime stress used an integration image containing wqueue: Support custom user work queues. #19982 and
  testing/ostest: Exercise custom work queues. nuttx-apps#3759 as the workload. Those PRs are test dependencies,
  not code dependencies of this change.

Build output:

Protected kernel:
  kflash  877528 B / 896 KB (95.64%)
  ksram    54320 B / 128 KB (41.44%)

Protected user:
  uflash  751000 B / 1 MB   (71.62%)
  usram     8192 B / 384 KB (2.08%)

Runtime stress results:

Protected libc user WQ: 15.6540 / 15.6540 / 15.6540 s
Protected kernel WQ:    30.1490 / 30.1480 / 30.1480 s

Steady current memory after initial run:
  Kmem used/free: 10104 / 243848 B
  Umem used/free:  9232 / 416752 B

The tests repeatedly exercised pthread creation, mutex/semaphore atomics,
multi-worker queues, synchronous cancellation, and queue teardown. All runs
completed without assertion, fault, residual worker, or cumulative Kmem/Umem
growth. The board cold-booted into NSH and remained stable.

Validation:

tools/checkpatch.sh -m -g upstream/master..fix/stm32h7-protected-memory: pass
tools/checkpatch.sh -g upstream/master..fix/stm32h7-protected-memory: pass
git diff --check upstream/master..fix/stm32h7-protected-memory: pass

PR verification Self-Check

• This PR introduces only one functional change.
• I have updated all required description fields above.
• My PR adheres to the contributing guidelines and coding standard.
• My PR is still work in progress.
• My PR is ready for review and can be safely merged.

[github-actions]

MemBrowse Memory Report

No memory changes detected for:

• arduino-mega2560
• esp32-devkitc
• hifive1-revb
• mirtoo
• qemu-armv8a
• qemu-intel64
• rx65n-rsk2mb
• s698pm-dkit
• stm32-nucleo-f103rb

[xiaoxiang781216]

ci was fixed, please rebase your change to the last master. @13022591351

[13022591351]

@xiaoxiang781216 Rebased onto the latest master (c6b349b023). The two patches are unchanged according to git range-diff, and tools/checkpatch.sh -g upstream/master..HEAD passes. The new CI run has started. Thanks.