RISC-V hardware with vector extension is readily available. Please, use vector intrinsics as described in https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/v0.11.x/rvv-intrinsic-api.md if `__riscv_v` is defined.
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lemire commentedon Dec 16, 2025
Would you be willing to prepare a pull request ?
Testing and reviewing is not a problem but someone needs to write the code.