Cortex-M: make quantized add and multiply layout-agnostic

[rascani]

Derive the channel-broadcast repeat length from the broadcast operand's element
count instead of a hard-coded channel dimension, so one pair of operators serves
both the legacy NCHW-logical channels-last contract and the NHWC-logical
contiguous one.

The kernels already read identical bytes under either contract; only the shape
metadata placed channels at a different index. Consult the dim order of the
larger operand rather than sniffing the shape, which stays correct when the
broadcast operand's unit dimensions leave its own dim order ambiguous. The
quantizer keeps asking the logical NCHW question it asked before, since it runs
ahead of any layout transform.

Cortex-M55 FVP add and multiply suites, the explicit-NHWC runtime cases, host
layout-parity coverage comparing both contracts through one operator, and
lintrunner.

Authored with Codex.

[rascani]

Stack from ghstack (oldest at bottom):

• Cortex-M: add an opt-in NHWC method I/O contract #22029
• Cortex-M: keep NHWC channel broadcasts quantized #21968
• Cortex-M: add opt-in explicit layout lowering #21967
• -> Cortex-M: make quantized add and multiply layout-agnostic #21966
• Cortex-M: add a contiguous-layout pad operator #22028
• Cortex-M: add explicit-NHWC runtime operators #21965
• Cortex-M: share layout-aware CMSIS-NN kernels #21964
• Channels last: add the common layout pipeline #21963
• Channels last: absorb boundary layout copies into the method contract #22034
• Channels last: optimize structural layout regions #21962
• Channels last: teach the data-movement passes both permute dialects #22003

[pytorch-bot]

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