Skip to content

Backport geni se core changes to qcom-6.18.y kernel branch - #959

Open
Aniket Randive (AniketRandive-coder) wants to merge 8 commits into
qualcomm-linux:qcom-6.18.yfrom
AniketRandive-coder:backport_geni_se_core
Open

Backport geni se core changes to qcom-6.18.y kernel branch#959
Aniket Randive (AniketRandive-coder) wants to merge 8 commits into
qualcomm-linux:qcom-6.18.yfrom
AniketRandive-coder:backport_geni_se_core

Conversation

@AniketRandive-coder

@AniketRandive-coder Aniket Randive (AniketRandive-coder) commented Aug 17, 2026

Copy link
Copy Markdown

Changes included:

  1. Refactor geni_icc_get() to make the qup-memory ICC path optional,
    improving compatibility with platforms that don't define it in DT.

  2. Add geni_icc_set_bw_ab() helper to set average bandwidth for all
    ICC paths in a single call, reducing code duplication across drivers.

  3. Introduce geni_se_resources_init() to centralize clock, OPP table,
    and ICC initialization that was previously duplicated across I2C,
    SPI, and UART drivers.

  4. Move core_clk management into geni_se_clks_on/off() so protocol
    drivers no longer need to handle this clock individually.

  5. Add geni_se_resources_activate() and geni_se_resources_deactivate()
    helpers to centralize runtime PM resource management across drivers.

  6. Add geni_se_domain_attach() helper to centralize power domain
    (power + perf) attachment for SA8255p platforms.

  7. Add geni_se_set_perf_level() and geni_se_set_perf_opp() helpers for
    performance level management via PM domains.

  8. Add geni_se_regs tracepoint to capture a full hardware register
    snapshot in a single trace record for post-mortem debugging of
    GENI SE-based driver failures (I2C, SPI, UART).

These are prerequisite changes required before backporting the
corresponding UART (PR1), SPI (PR2), and I2C (PR3) driver updates.

CRs-Fixed: 4642708

@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: Refactor geni_icc_get() and make qup-me…
b2a4151 
…mory ICC path optional

The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.

The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optional and
skipped when not present in the device tree.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
[...]
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-2-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
2ee9a18 
Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.

This provides a more convenient API for drivers that need to configure
specific average bandwidth values.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-3-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
BACKPORT: soc: qcom: geni-se: Introduce helper API for resource initi…
333823c 
…alization

The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.

Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-4-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: Handle core clk in geni_se_clks_off() a…
adaca6b 
…nd geni_se_clks_on()

Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.

Core clk is now properly managed alongside the other clocks (se->clk
and wrapper clocks) in the fundamental clock control functions,
eliminating the need for individual protocol drivers to handle this
clock separately.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-5-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: Add resources activation/deactivation h…
2110393 
…elpers

The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.

Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactivate function disables resources in reverse order
including OPP rate reset, clocks, ICC and TLMM.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-6-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
BACKPORT: soc: qcom: geni-se: Introduce helper API for attaching powe…
fc7382c 
…r domains

The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.

Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE
device.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-7-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: Introduce helper APIs for performance c…
fd2bc07 
…ontrol

The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.

Introduce two new helper APIs, geni_se_set_perf_level() and
geni_se_set_perf_opp(), addresses this issue by providing a streamlined
method for the GENI Serial Engine (SE) drivers to find and set the OPP
based on the desired performance level, thereby eliminating redundancy.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-8-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
@ptalari27 Aniket Randive
UPSTREAM: soc: qcom: geni-se: trace: Add trace event support for GENI…
344a30b 
… SE registers dump

Diagnosing GENI SE-based driver (serial, SPI, I2C) failures currently
requires reading each hardware register individually, either through
ad hoc debug code or a debugger. This is slow, requires the state to
remain stable across the multiple reads, and cannot be run
non-intrusively during normal operation without adding printk-style
noise to each driver.

Add a new trace event header for the Qualcomm GENI Serial Engine (SE)
framework providing a geni_se_regs tracepoint. This tracepoint
captures a comprehensive snapshot of the GENI SE hardware state in a
single trace record, making it possible to correlate register values at
a precise point in time without multiple sequential reads.

The trace event records the following register groups:

 - Main/secondary command and IRQ status (M_CMD0, S_CMD0, M/S_IRQ_STATUS)
 - Engine status, IOS, and command control/error registers
 - TX/RX FIFO status and watermark registers (including RFR watermark)
 - M/S GP length registers
 - DMA TX/RX IRQ, enable, length, pointer, attribute, and burst registers
 - DMA interface enable, general config, QSB trans config, and debug
 - M/S IRQ enable, GSI event enable, and top-level SE IRQ enable
 - Serial master/slave clock config, general config, output control,
   clock control RO, FIFO interface disable, and FW multilock MSA
 - Clock select register

Having all these registers captured atomically in a single ftrace record
allows drivers built on top of the GENI SE framework (serial, SPI, I2C)
to invoke this tracepoint on error paths and reconstruct the full engine
state during post-mortem analysis without instrumenting each driver
separately.

Acked-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Link: https://patch.msgid.link/20260729-add-tracepoints-for-se-reg-dump-v4-1-08bbd63b0ed2@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
@qswat-orbit-external

qswat-orbit-external Bot commented Aug 17, 2026

Copy link
Copy Markdown

Merge Check Failed: CR Not Eligible for Merge

CR 4642708 is not eligible for merge.

The parent software image for kernel.qli.2.0 is not development complete.

Entity: kernel.qli.2.0
CR: 4642708
Reason: CR_CANNOT_MERGE

Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations.

@AniketRandive-coder

Aniket Randive (AniketRandive-coder) commented Aug 17, 2026

Copy link
Copy Markdown
Author

Merge Check Failed: CR Not Eligible for Merge

CR 4642708 is not eligible for merge.

The parent software image for kernel.qli.2.0 is not development complete.

Entity: kernel.qli.2.0 CR: 4642708 Reason: CR_CANNOT_MERGE

Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations.

cr is now in dev-complete state

@AniketRandive-coder

Aniket Randive (AniketRandive-coder) commented Aug 17, 2026

Copy link
Copy Markdown
Author

is there any way to rerun the Change Requests Validation Check?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@lumag Dmitry Baryshkov (lumag) Awaiting requested review from lumag lumag was automatically assigned from qualcomm-linux/qualcomm-kernel-maint
@quicAspratap Shivendra Pratap (quicAspratap) Awaiting requested review from quicAspratap quicAspratap was automatically assigned from qualcomm-linux/qualcomm-kernel-maint
@sgaud-quic Salendarsingh Gaud (sgaud-quic) Awaiting requested review from sgaud-quic sgaud-quic was automatically assigned from qualcomm-linux/qualcomm-kernel-maint

At least 1 approving review is required to merge this pull request.

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@AniketRandive-coder @ptalari27