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add core::arch::{x86, x86_64}::x87_f80 - #163992

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folkertdev:x87_f80-simple
Nov 10, 2026
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rust-bors[bot] merged 6 commits into
rust-lang:mainfrom
folkertdev:x87_f80-simple

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@folkertdev folkertdev commented Oct 8, 2026 •

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tracking issue: #163982
cc #161787

Add x87_f80 in the same way as f16b and ppcf128.


It's unclear what to do with this type on softfloat targets. Clang and GCC reject the type when the x87 registers are not available. We should do the same, probably just with a cfg?

I don't think we have a good cfg for this though? x87 is still set on softfloat targets, while soft-float doesn't get set (that does not give a warning even, it probably should?). We also don't set cfg_abi.

future work

  • the ABI of Complex<x87_f80> has not yet been implemented
  • x87_f80 does not yet implement VaArgSafe

@folkertdev folkertdev added the F-c_longdouble `#![feature(c_longdouble)]` label Oct 8, 2026
@rustbot rustbot added A-attributes Area: Attributes (`#[…]`, `#![…]`) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. A-test-infra-minicore Area: `minicore` test auxiliary and `//@ add-minicore` S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Oct 8, 2026
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r? beetrees
cc @tgross35 @RalfJung

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folkertdev marked this pull request as ready for review October 8, 2026 19:07
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stdarch is developed in its own repository. If possible, consider making this change to rust-lang/stdarch instead.

cc @Amanieu, @sayantn

Some changes occurred in compiler/rustc_attr_ir

cc @jdonszelmann, @JonathanBrouwer

rustc_codegen_cranelift is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_cranelift instead.

cc @bjorn3

Some changes occurred to the CTFE / Miri interpreter

cc @rust-lang/miri

Some changes occurred to the CTFE machinery

cc @RalfJung, @oli-obk, @lcnr

This PR changes rustc_public

cc @oli-obk, @celinval, @ouz-a, @makai410

rustc_codegen_gcc is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_gcc instead.

cc @antoyo, @GuillaumeGomez

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Oct 8, 2026
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@bors try jobs=test-various,test-i686-*

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rust-bors Bot pushed a commit that referenced this pull request Oct 8, 2026
add `core::arch::{x86, x86_64}::x87_f80`


try-job: test-various
try-job: test-i686-*
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☀️ Try build successful (CI)
Build commit: 4923e95 (4923e95bc1c5973505d6b35dcddbc97d11ae69e5)
Base parent: 65efa19 (65efa194201c67ba29b7384255a534d61c2aa3cb)

@RalfJung

RalfJung commented Oct 9, 2026 •

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This changes the signature of size because the size of x87_f80 depends on the target (12 bytes on 32-bit targets, 16 bytes on 64-bit targets).

"f80" is 128 bits large on 64-bit targets...?!?? How does that make any sense?

It also breaks an invariant that scalars are the size of their fields: the x87_f80 scalar is 80 bits, but the field is the aforementioned 12 or 16 bytes. Let's hope we don't subtly rely on that somewhere.

I'd be surprised if we didn't. That's been pretty much part of the definition of being a scalar -- if a type has padding, it is not a scalar type. The interpreter was built around that assumption.
Cc @scottmcm who recently generalized what a scalar can be, but even with that I don't think it can have padding.

It does not sound to me like this type can be a scalar, then.

Comment on lines +600 to +607
// For `x87_f80` the primitive is 80 bits, but the field (after rounding up to
// the alignment) is 12 bytes (on 32-bit systems) or 16 bytes (64-bit).
// So we can't assert equality of size and layout.size.
assert_eq!(
size.align_to(s.default_align(self).abi),
mplace.layout.size,
"abi::Scalar is larger than its layout"
);

@RalfJung RalfJung Oct 9, 2026 •

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The entire logic for dealing with scalars throughout the interpreter assumes that they have no padding. Changing this assertion is not enough, it just means the rest of the interpreter is now more or less silently wrong. Pretty much all codepaths that deal with scalars need to be audited. Same for every other MIR consumer.

I would strongly prefer if we didn't break the fundamental concept of a "scalar".

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To give just one example, here's one place we make that assumption:

Immediate::Scalar(scalar) => {
alloc.write_scalar(alloc_range(Size::ZERO, scalar.size()), scalar)?;
}

You can't even see it. But if you look at the ScalarPair path you can see that we have to ensure that padding gets reset to uninit, and in the Scalar path we don't have to worry about that.

Also, the basic APIs for reading/writing stuff in an Allocation are read_scalar/write_scalar. This again uses the term "scalar" to refer to something that has no padding. Same for the type Scalar. And so on.

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RalfJung commented Oct 9, 2026 •

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It would probably be possible, with a lot of effort, to fix all the places where we assume scalars have no padding. But I think that's a bad idea. It makes life harder for every MIR consumer. (Most likely it'll mean many MIR consumers will stay buggy as nobody will expect something as outlandish as this weird type.) This new type is the weird one here, we should not shape everything around a legacy type that hardly anyone needs and that has no justification to exist in the first place other than "it has always been here".

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beetrees commented Oct 9, 2026

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I think it might make sense to introduce something like BackendRepr::PaddedScalar (name bikesheddable)? This would be useful for more than just x87_f80: e.g. currently we can (don't have my laptop to check if we currently do) represent #[repr(align(16))] struct A(u8, u8); as a BackendRepr::ScalarPair, whereas #[repr(align(16))] struct A(u8); currently has to be represented as BackendRepr::Memory as it has padding.

@tgross35

tgross35 commented Oct 9, 2026

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For Rust's purposes could we just pretend it's a MaybeUninit<u128> on x86-64 rather than treating it as a padded scalar?

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folkertdev force-pushed the x87_f80-simple branch 2 times, most recently from 16dc967 to 27fa2c7 Compare November 5, 2026 18:37
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This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

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beetrees commented Nov 9, 2026

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r=me once r? @RalfJung gives a LGTM on the const eval/Miri stuff.

@rustbot rustbot assigned RalfJung and unassigned beetrees Nov 9, 2026
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RalfJung is not on the review rotation at the moment.
They may take a while to respond.

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RalfJung commented Nov 9, 2026

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@bors r=beetrees,RalfJung

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📌 Commit 7274b42 has been approved by beetrees,RalfJung

It is now in the queue for this repository.

@rust-bors rust-bors Bot added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Nov 9, 2026
jhpratt added a commit to jhpratt/rust that referenced this pull request Nov 10, 2026
…ees,RalfJung

add `core::arch::{x86, x86_64}::x87_f80`

tracking issue: rust-lang#163982
cc rust-lang#161787

Add `x87_f80` in the same way as `f16b` and `ppcf128`.

---

It's unclear what to do with this type on softfloat targets. Clang and GCC reject the type when the x87 registers are not available. We should do the same, probably just with a `cfg`?

I don't think we have a good `cfg` for this though? `x87` is still set on softfloat  targets, while `soft-float` doesn't get set (that does not give a warning even, it probably should?). We also don't set `cfg_abi`.

### future work

- the ABI of `Complex<x87_f80>` has not yet been implemented
- `x87_f80` does not yet implement `VaArgSafe`
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Note

This PR was benchmarked as part of triage of its containing rollup: triage URL.

Finished benchmarking commit (ff26eab): comparison URL.

Overall result: ❌✅ regressions and improvements - please read:

Our benchmarks found a performance regression caused by this PR.
This might be an actual regression, but it can also be just noise.

Next Steps:

  • If the regression was expected or you think it can be justified,
    please write a comment with sufficient written justification, and add
    @rustbot label: +perf-regression-triaged to it, to mark the regression as triaged.
  • If you think that you know of a way to resolve the regression, try to create
    a new PR with a fix for the regression.
  • If you do not understand the regression or you think that it is just noise,
    you can ask the @rust-lang/wg-compiler-performance working group for help (members of this group
    were already notified of this PR).

@rustbot label: +perf-regression
cc @rust-lang/wg-compiler-performance

Instruction count

Our most reliable metric. Used to determine the overall result above. However, even this metric can be noisy.

mean range count
Regressions ❌
(primary)
0.2% [0.2%, 0.2%] 3
Regressions ❌
(secondary)
- - 0
Improvements ✅
(primary)
-0.2% [-0.3%, -0.2%] 4
Improvements ✅
(secondary)
- - 0
All ❌✅ (primary) -0.0% [-0.3%, 0.2%] 7

Max RSS (memory usage)

Results (primary 2.1%)

A less reliable metric. May be of interest, but not used to determine the overall result above.

mean range count
Regressions ❌
(primary)
2.1% [2.1%, 2.1%] 1
Regressions ❌
(secondary)
- - 0
Improvements ✅
(primary)
- - 0
Improvements ✅
(secondary)
- - 0
All ❌✅ (primary) 2.1% [2.1%, 2.1%] 1

Cycles

This perf run didn't have relevant results for this metric.

Binary size

This perf run didn't have relevant results for this metric.

Artifact size: 406.28 MiB -> 406.35 MiB (0.02%)

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