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Allow disabling ML-DSA AVX2/512 specifically with WC_MLDSA_NO_AVX2. Disable AVX512 AES code with NO_VAES_SUPPORT, as it is also VAES. #11931

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Allow disabling ML-DSA AVX2/512 specifically with WC_MLDSA_NO_AVX2. Disable AVX512 AES code with NO_VAES_SUPPORT, as it is also VAES. #11931

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464a290
Allow disabling ML-DSA AVX2/512 specifically with WC_MLDSA_NO_AVX2.
kareem-wolfssl Oct 29, 2026
65300bb
Don't build the AVX512 VAES AES kernels with NO_VAES_SUPPORT defined.
kareem-wolfssl Oct 30, 2026
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1 change: 1 addition & 0 deletions .wolfssl_known_macro_extras
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Expand Up @@ -847,6 +847,7 @@ WC_LINUXKM_NO_USE_HEAP_WRAPPERS
WC_LINUXKM_SPIN_IN_ATOMIC
WC_LINUXKM_FORCE_SVR_DYNAMIC_AUDITING
WC_MLDSA_NO_ASM
WC_MLDSA_NO_AVX2
WC_MLKEM_KERNEL_ASM
WC_MPFS_ATHENA_NO_BASE_ADDR
WC_MPFS_ATHENA_NO_HW_INIT
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2 changes: 1 addition & 1 deletion linuxkm/lkcapi_aes_glue.c
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Expand Up @@ -108,7 +108,7 @@
#define WOLFKM_AESCMAC_NAME "cmac(aes)"

#if defined(WOLFSSL_X86_64_BUILD) && (defined(USE_INTEL_SPEEDUP) || defined(USE_INTEL_SPEEDUP_FOR_AES))
#if !defined(NO_AVX512_SUPPORT)
#if !defined(NO_AVX512_SUPPORT) && !defined(NO_VAES_SUPPORT)
#define WOLFKM_AES_DRIVER_ISA_EXT "-vaes-avx512"
#elif !defined(NO_VAES_SUPPORT)
#define WOLFKM_AES_DRIVER_ISA_EXT "-vaes-avx2"
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10 changes: 6 additions & 4 deletions wolfcrypt/src/aes.c
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Expand Up @@ -968,7 +968,9 @@ static WC_INLINE void wc_Stm32_CrypAesBlock(const byte* in, byte* out)
#if !defined(NO_VAES_SUPPORT) && !defined(HAVE_INTEL_VAES)
#define HAVE_INTEL_VAES
#endif
#if !defined(NO_AVX512_SUPPORT) && !defined(HAVE_INTEL_AVX512)
/* The AVX512 AES kernels are VAES code. */
#if !defined(NO_VAES_SUPPORT) && !defined(NO_AVX512_SUPPORT) && \
!defined(HAVE_INTEL_AVX512)
#define HAVE_INTEL_AVX512
#endif
Comment on lines +971 to 975

@claude claude Bot Oct 29, 2026

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🟣 pre-existing, not blocking: pre-existing, partial fix: builds with NO_VAES_SUPPORT still assemble the AVX512 VAES AES kernels. Only aes.c and the linuxkm glue were updated. aes_gcm_asm.S:40-44 and aes_xts_asm.S:40-44 still define HAVE_INTEL_AVX512 whenever NO_AVX512_SUPPORT is unset. Fix: in every generated AES asm file, define HAVE_INTEL_AVX512 only when NO_VAES_SUPPORT is also unset, as aes.c now does. That covers the .S files plus their .asm and x86 variants, and is best done in the asm generator so it survives regeneration. [also at: wolfcrypt/src/aes.c:974 - Builds with NO_VAES_SUPPORT still assemble the VAES AVX512 XTS kernels, so a toolchain without VAES support still fails.]
A small fix can ride a push you are already making; otherwise a short reply is enough.

Why this was flagged

A user defines NO_VAES_SUPPORT but leaves NO_AVX512_SUPPORT unset, typically because their assembler or target cannot handle VAES. aes.c:971-975 now leaves HAVE_INTEL_AVX512 undefined, so the C code no longer calls the AVX512 kernels. aes_gcm_asm.S:40-44 and aes_xts_asm.S:40-44 still define HAVE_INTEL_AVX512 independently of NO_VAES_SUPPORT. The AVX512 VAES blocks at aes_gcm_asm.S:26236-37242 and aes_xts_asm.S:4993-7233 are therefore still assembled. An assembler without VAES support still fails exactly as on the base branch. With a capable assembler, the binary ships about 13k lines of unreachable VAES code. The PR title promises to disable the AVX512 AES code with NO_VAES_SUPPORT, but that only holds on the C side.

Verification: Trigger: a build that defines NO_VAES_SUPPORT, leaves NO_AVX512_SUPPORT unset, and uses an assembler that does not know VAES. aes_gcm_asm.S:40-44 and aes_xts_asm.S:40-44 still have their own #ifndef NO_AVX512_SUPPORT / #define HAVE_INTEL_AVX512, with no check of NO_VAES_SUPPORT. So the VAES AVX512 blocks are still assembled. The base branch fails the same way by the same route.


Expand Down Expand Up @@ -9138,9 +9140,9 @@ void GenerateM0(Gcm* gcm)
#ifdef WOLFSSL_X86_64_BUILD
#ifndef NO_VAES_SUPPORT
#define HAVE_INTEL_VAES
#endif
#ifndef NO_AVX512_SUPPORT
#define HAVE_INTEL_AVX512
#ifndef NO_AVX512_SUPPORT
#define HAVE_INTEL_AVX512
#endif
#endif
#endif
#endif
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2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_gcm_asm.S
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Expand Up @@ -26232,7 +26232,6 @@ L_AES_GCMSIV_ctr_vaes_done_enc:
.size AES_GCMSIV_ctr_vaes,.-AES_GCMSIV_ctr_vaes
#endif /* __APPLE__ */
#endif /* WOLFSSL_AESGCM_SIV */
#endif /* HAVE_INTEL_VAES */
#ifdef HAVE_INTEL_AVX512
#ifndef __APPLE__
.data
Expand Down Expand Up @@ -37240,6 +37239,7 @@ L_AES_GCMSIV_ctr_avx512_done_enc:
#endif /* __APPLE__ */
#endif /* WOLFSSL_AESGCM_SIV */
#endif /* HAVE_INTEL_AVX512 */
#endif /* HAVE_INTEL_VAES */
#endif /* WOLFSSL_X86_64_BUILD */

#if defined(__linux__) && defined(__ELF__)
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2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_gcm_asm.asm
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Expand Up @@ -27054,7 +27054,6 @@ ELSE
_TEXT ENDS
ENDIF
ENDIF
ENDIF
IFDEF HAVE_INTEL_AVX512
IF fips_version GE 7
fipsBb SEGMENT READONLY ALIAS(".fipsB$b") 'CONST'
Expand Down Expand Up @@ -38322,4 +38321,5 @@ _TEXT ENDS
ENDIF
ENDIF
ENDIF
ENDIF
END
2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_x86_64_asm.S
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Expand Up @@ -3608,7 +3608,6 @@ L_AES_CTR_encrypt_vaes_done_enc:
#ifndef __APPLE__
.size AES_CTR_encrypt_vaes,.-AES_CTR_encrypt_vaes
#endif /* __APPLE__ */
#endif /* HAVE_INTEL_VAES */
#ifdef HAVE_INTEL_AVX512
#ifndef __APPLE__
.text
Expand Down Expand Up @@ -5099,6 +5098,7 @@ L_AES_CTR_encrypt_avx512_done_enc:
.size AES_CTR_encrypt_avx512,.-AES_CTR_encrypt_avx512
#endif /* __APPLE__ */
#endif /* HAVE_INTEL_AVX512 */
#endif /* HAVE_INTEL_VAES */
#endif /* WOLFSSL_X86_64_BUILD */

#if defined(__linux__) && defined(__ELF__)
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2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_x86_64_asm.asm
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Expand Up @@ -3737,7 +3737,6 @@ fipsAb ENDS
ELSE
_TEXT ENDS
ENDIF
ENDIF
IFDEF HAVE_INTEL_AVX512
IF fips_version GE 7
fipsAb SEGMENT ALIAS(".fipsA$b") 'CODE'
Expand Down Expand Up @@ -5325,4 +5324,5 @@ ELSE
_TEXT ENDS
ENDIF
ENDIF
ENDIF
END
2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_xts_asm.S
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Expand Up @@ -4989,7 +4989,6 @@ L_AES_XTS_decrypt_update_vaes_done_dec:
#ifndef __APPLE__
.size AES_XTS_decrypt_update_vaes,.-AES_XTS_decrypt_update_vaes
#endif /* __APPLE__ */
#endif /* HAVE_INTEL_VAES */
#ifdef HAVE_INTEL_AVX512
#ifndef __APPLE__
.text
Expand Down Expand Up @@ -7231,6 +7230,7 @@ L_AES_XTS_decrypt_update_avx512_done_dec:
.size AES_XTS_decrypt_update_avx512,.-AES_XTS_decrypt_update_avx512
#endif /* __APPLE__ */
#endif /* HAVE_INTEL_AVX512 */
#endif /* HAVE_INTEL_VAES */
#endif /* WOLFSSL_X86_64_BUILD */
#endif /* WOLFSSL_AES_XTS */

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2 changes: 1 addition & 1 deletion wolfcrypt/src/aes_xts_asm.asm
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Expand Up @@ -5224,7 +5224,6 @@ fipsAb ENDS
ELSE
_TEXT ENDS
ENDIF
ENDIF
IFDEF HAVE_INTEL_AVX512
IF fips_version GE 7
fipsAb SEGMENT ALIAS(".fipsA$b") 'CODE'
Expand Down Expand Up @@ -7565,4 +7564,5 @@ ELSE
_TEXT ENDS
ENDIF
ENDIF
ENDIF
END
8 changes: 8 additions & 0 deletions wolfcrypt/src/wc_mldsa.c
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Expand Up @@ -265,6 +265,14 @@
#if defined(USE_INTEL_SPEEDUP)
static cpuid_flags_t cpuid_flags = WC_CPUID_INITIALIZER;

/* Keep the BMI2 Keccak and drop all AVX2/AVX512 code. */
#ifdef WC_MLDSA_NO_AVX2
#undef IS_INTEL_AVX2
#define IS_INTEL_AVX2(f) 0
#undef SHA3_USE_AVX2
#define SHA3_USE_AVX2(f) 0
#endif

/* AVX2 NTT/invNTT flavor selection: the non-full AVX2 NTT/invNTT keep the
* NTT-domain coefficients in a permuted (lane-interleaved) order that only
* the non-full AVX2 consumers understand, whereas the full variants and the
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2 changes: 1 addition & 1 deletion wolfssl/wolfcrypt/wc_mldsa.h
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Expand Up @@ -929,7 +929,7 @@ WOLFSSL_API int wc_MlDsaKey_PrivateKeyToDer(wc_MlDsaKey* key, byte* output,
/* AVX512 assembly for ML-DSA is built (and dispatched at runtime on capable
* CPUs) whenever the Intel speedups are enabled and AVX512 is not opted out.
* Matches the HAVE_INTEL_AVX512 guard around the generated assembly. */
#ifndef NO_AVX512_SUPPORT
#if !defined(NO_AVX512_SUPPORT) && !defined(WC_MLDSA_NO_AVX2)
#define WOLFSSL_MLDSA_HAVE_INTEL_AVX512
/* AVX512VBMI (vpermb) functions are built (matching the auto-enabled
* HAVE_INTEL_AVX512_VBMI guard around the generated assembly) and
Expand Down
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