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Pull requests: UCSBarchlab/PyRTL
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Remove unnecessary slice (
s) LogicNets from sign_extended and zero_extended.
#496
opened Jul 16, 2026 by
fdxmw
Contributor
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ConsecutiveSlice optimizations to CompiledSimulation for ~46% reduction in compile time.
#495
opened Jul 15, 2026 by
fdxmw
Contributor
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name_scope is a context manager that prepends prefixes to WireVector and MemBlock names
#492
opened Jul 11, 2026 by
fdxmw
Contributor
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Deploy GitHub pages from GitHub actions with Sphinx
#489
opened Jun 24, 2026 by
fdxmw
Contributor
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Implement a language agnostic hardware representation
#404
opened Sep 21, 2021 by
RhysGretsch81
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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
#398
opened Jul 9, 2021 by
mdko
Contributor
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