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Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended.#496

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fdxmw wants to merge 5 commits into
UCSBarchlab:developmentfrom
fdxmw:extend
Open

Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended.#496
fdxmw wants to merge 5 commits into
UCSBarchlab:developmentfrom
fdxmw:extend

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@fdxmw

@fdxmw fdxmw commented Jul 16, 2026

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This removes 9% of pyrtlnet's slice (s) LogicNets, and 6% of pyrtlnet's wire (W) WireVectors, without introducing any new LogicNets or WireVectors. This speeds up simulation times, especially with pyrtl.Simulation.

Fix tests broken by this change.

…zero_extended`.

This removes 9% of pyrtlnet's slice (`s`) `LogicNets`, and 6% of pyrtlnet's
wire (`W`) `WireVectors`, without introducing any new `LogicNets` or
`WireVectors`. This speeds up simulation times, especially with `pyrtl.Simulation`.

Fix tests broken by this change.
@codecov

codecov Bot commented Jul 16, 2026

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 92.1%. Comparing base (1c9ce1f) to head (b1889b8).

Additional details and impacted files
@@              Coverage Diff              @@
##           development    #496     +/-   ##
=============================================
- Coverage         92.2%   92.1%   -0.0%     
=============================================
  Files               30      30             
  Lines             7465    7462      -3     
=============================================
- Hits              6876    6872      -4     
- Misses             589     590      +1     

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fdxmw added 4 commits July 16, 2026 09:30
We lost coverage for this case because `sign_extended` no longer generates
slices that copy the most significant bit.
…e bit multiple times.

This case no longer occurs now that `sign-extended` `concats` multiple copies
of the most significant bit.
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