Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended.

pyrtl/importexport.py

@@ -1176,9 +1176,6 @@ def _verilog_expr(self, gate: Gate, lhs: Gate | None = None) -> str:
                     selections.append(f"{verilog_args[0]}[{sel}]")
             if len(gate.sel) == 1:
                 return f"({selections[0]})"
-            # Special case: slicing multiple copies of the same gate.
-            if all(sel == gate.sel[0] for sel in gate.sel):
-                return f"{{{len(selections)} {{{selections[0]}}}}}"
             # Special case: slicing a consecutive subset.
             if tuple(range(gate.sel[0], gate.sel[-1] + 1)) == gate.sel:
                 return f"({verilog_args[0]}[{gate.sel[-1]}:{gate.sel[0]}])"

pyrtl/visualization.py

@@ -269,10 +269,6 @@ def label(v):
                 bits = f"[{selLower}]"
             elif node.op_param == tuple(range(selLower, selUpper + 1)):  # consecutive
                 bits = f"[{selUpper}:{selLower}]"
-            elif all(
-                ix == node.op_param[0] for ix in node.op_param[1:]
-            ):  # all the same
-                bits = f"[{node.op_param[0]}]*{len(node.op_param)}"
             else:
                 bits = "bits" + str(tuple(reversed(node.op_param)))
             return f'[label="{label(bits)}", fillcolor=azure1, height=.25, width=.25]'

pyrtl/wire.py

@@ -1400,7 +1400,18 @@ def sign_extended(self, bitwidth) -> WireVector:
         :raises PyrtlError: If the ``bitwidth`` specified is smaller than
             :attr:`bitwidth`.
         """
-        return self._extend_with_bit(bitwidth, self[-1])
+        num_added_bits = bitwidth - self.bitwidth
+        if num_added_bits == 0:
+            return self
+        if num_added_bits < 0:
+            msg = "sign_extended can not reduce the number of bits"
+            raise PyrtlError(msg)
+
+        from pyrtl.corecircuits import concat
+
+        sign_bit = self[-1]
+
+        return concat(*([sign_bit] * num_added_bits), self)
 
     def zero_extended(self, bitwidth) -> WireVector:
         """Return a zero-extended copy of ``self``.
@@ -1433,27 +1444,16 @@ def zero_extended(self, bitwidth) -> WireVector:
         :raises PyrtlError: If the ``bitwidth`` specified is smaller than
             :attr:`bitwidth`.
         """
-        return self._extend_with_bit(bitwidth, 0)
-
-    def _extend_with_bit(self, bitwidth, extbit):
-        numext = bitwidth - self.bitwidth
-        if numext == 0:
+        num_added_bits = bitwidth - self.bitwidth
+        if num_added_bits == 0:
             return self
-        if numext < 0:
-            msg = (
-                "Neither zero_extended nor sign_extended can reduce the number of bits"
-            )
+        if num_added_bits < 0:
+            msg = "zero_extended can not reduce the number of bits"
             raise PyrtlError(msg)
+
         from pyrtl.corecircuits import concat
 
-        if isinstance(extbit, int):
-            extbit = Const(extbit, bitwidth=1)
-        extvector = WireVector(bitwidth=numext)
-        net = LogicNet(
-            op="s", op_param=(0,) * numext, args=(extbit,), dests=(extvector,)
-        )
-        working_block().add_net(net)
-        return concat(extvector, self)
+        return concat(Const(0, bitwidth=num_added_bits), self)
 
 
 WireVectorLike = WireVector | int | str | bool

tests/test_analysis.py

@@ -156,34 +156,34 @@ def setUp(self):
 From i
   To o
     Path 0
-      tmp5/3W <-- - -- i/2I, tmp4/2W
-      tmp6/3W <-- | -- tmp2/3W, tmp5/3W
-      o/3O <-- w -- tmp6/3W
+      tmp3/3W <-- - -- i/2I, tmp2/2W
+      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
+      o/3O <-- w -- tmp4/3W
     Path 1
-      tmp1/3W <-- c -- tmp0/1W, i/2I
-      tmp2/3W <-- & -- tmp1/3W, j/3I
-      tmp6/3W <-- | -- tmp2/3W, tmp5/3W
-      o/3O <-- w -- tmp6/3W
+      tmp0/3W <-- c -- const_0_0/1C, i/2I
+      tmp1/3W <-- & -- tmp0/3W, j/3I
+      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
+      o/3O <-- w -- tmp4/3W
   To p
     Path 0
-      tmp8/4W <-- c -- tmp7/2W, i/2I
-      tmp9/5W <-- - -- k/4I, tmp8/4W
-      p/5O <-- w -- tmp9/5W
+      tmp5/4W <-- c -- const_3_0/2C, i/2I
+      tmp6/5W <-- - -- k/4I, tmp5/4W
+      p/5O <-- w -- tmp6/5W
 From j
   To o
     Path 0
-      tmp2/3W <-- & -- tmp1/3W, j/3I
-      tmp6/3W <-- | -- tmp2/3W, tmp5/3W
-      o/3O <-- w -- tmp6/3W
+      tmp1/3W <-- & -- tmp0/3W, j/3I
+      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
+      o/3O <-- w -- tmp4/3W
   To p
     (No paths)
 From k
   To o
     (No paths)
   To p
     Path 0
-      tmp9/5W <-- - -- k/4I, tmp8/4W
-      p/5O <-- w -- tmp9/5W
+      tmp6/5W <-- - -- k/4I, tmp5/4W
+      p/5O <-- w -- tmp6/5W
 """
 
 
@@ -381,6 +381,7 @@ def test_pretty_print(self):
         paths = pyrtl.paths()
         output = io.StringIO()
         paths.print(file=output)
+        self.maxDiff = 30000
         self.assertEqual(output.getvalue(), paths_print_output)
 
 

tests/test_compilesim.py

@@ -221,9 +221,6 @@ class SimWithSpecialWiresBase(unittest.TestCase):
     def setUp(self):
         pyrtl.reset_working_block()
 
-    def test_reg_directly_before_reg(self):
-        pass
-
     def test_weird_wire_names(self):
         """Some simulations need to be careful when handling special names (eg Fastsim
         June 2016)

tests/test_core.py

@@ -73,9 +73,6 @@ def test_logicsubset_no_op(self):
         block = pyrtl.working_block()
         self.assertEqual(block.logic_subset(None), block.logic)
 
-    def test_sanity_check(self):
-        pass
-
     def test_block_iterators(self):
         # testing to see that it properly runs a trivial case
         inwire = pyrtl.Input(bitwidth=1, name="inwire1")
@@ -589,15 +586,6 @@ def test_string_format(self):
         net = pyrtl.LogicNet("+", "xx", ("arg1", "arg2"), ("dest",))
         self.assertEqual(str(net), "dest <-- + -- arg1, arg2 (xx)")
 
-    def test_net_with_wirevectors(self):
-        pass
-
-    def test_memory_read_print(self):
-        pass
-
-    def test_memory_write_print(self):
-        pass
-
     def test_self_equals(self):
         a = pyrtl.WireVector()
         b = pyrtl.WireVector()

tests/test_helperfuncs.py

@@ -28,9 +28,6 @@ def test_helperfuncs_doctests(self):
 
 
 class TestWireVectorList(unittest.TestCase):
-    def setUp(self):
-        pass
-
     def test_input_list_type(self):
         inputs = pyrtl.input_list("one, two, three")
         self.assertTrue(all(isinstance(inp, pyrtl.Input) for inp in inputs))
@@ -80,9 +77,6 @@ def test_wirevector_list_raise_errors(self):
 
 
 class TestNonCoreHelpers(unittest.TestCase):
-    def setUp(self):
-        pass
-
     def test_log2(self):
         self.assertEqual(pyrtl.log2(1), 0)
         self.assertEqual(pyrtl.log2(2), 1)